
Location: On Site in Rochester, NY, United States
Employment type: Full-time
Salary: $120,000 - $180,000 per year
Posted: 2 months ago
MissionHires is seeking an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. You will craft comprehensive verification plans, build self-checking SystemVerilog/UVM environments, drive functional coverage closure, and collaborate cross-functionally to ensure designs meet stringent system requirements. This role includes preparing and presenting technical reviews and may require the ability to obtain and maintain US Security Clearance.
MissionHires is the AI hiring partner of top talent teams. Our platform helps recruiters, agencies, and top companies source, engage with, and evaluate top talent 10 times faster than job boards.
To bridge the gap between companies and passionate talent.
It’s on-site in Rochester, NY.
Yes, paid relocation assistance is provided.
USD $120,000 to $180,000 per year.
Yes, you must be able to obtain and maintain US Security Clearance.
SystemVerilog with UVM/OVM, advanced functional coverage tools, and Mentor Graphics verification tools.
Building self-checking UVM/SystemVerilog testbenches, writing randomized and directed tests, driving functional coverage, and collaborating on embedded communication systems.
SystemVerilog, plus scripting in Bash, Perl, Python, or Tcl; OOP experience in C++ or Java is a plus.
Bachelor’s with 6+ years, or Master’s with 4+ years, or 10+ years relevant experience without a degree.