MissionHires

FPGA/ASIC Verification Engineer - Rochester, NY

Published

Location: On Site in Rochester, NY, United States

Employment type: Full-time

Salary: $120,000 - $180,000 per year

Posted: 2 months ago

Why This Role Matters

MissionHires is seeking an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. You will craft comprehensive verification plans, build self-checking SystemVerilog/UVM environments, drive functional coverage closure, and collaborate cross-functionally to ensure designs meet stringent system requirements. This role includes preparing and presenting technical reviews and may require the ability to obtain and maintain US Security Clearance.

How You'll Contribute

  • Perform FPGA/ASIC design verification and validation of embedded electronic communication systems
  • Develop high-level and detailed verification test plans aligned with system requirements and specifications
  • Create self-checking testbenches using SystemVerilog for verification and validation
  • Develop UVM/OVM components including agents, sequences, covergroups, predictors, and scoreboards
  • Author randomized and directed tests to achieve functional coverage goals and provide feedback to the team
  • Utilize advanced functional verification tools to collect and report functional coverage
  • Collaborate with cross-functional teams to define and verify product and design requirements
  • Analyze and debug FPGA firmware and related hardware issues
  • Prepare and conduct design and implementation reviews; deliver technical briefings and status updates to internal and external stakeholders
  • Work within Linux environments and leverage scripting to automate verification workflows

What Makes You a Great Fit

  • Bachelor’s degree with 6+ years of relevant experience, or a Master’s degree with 4+ years, or 10+ years of relevant experience in lieu of a degree
  • Experience developing and verifying FPGA/ASIC-based embedded system solutions
  • Proven proficiency in FPGA/ASIC verification using SystemVerilog
  • Working knowledge of UVM/OVM methodology and ability to build reusable verification components
  • Experience creating randomized and directed tests and driving functional coverage closure
  • Ability to analyze and debug FPGA firmware and related hardware
  • Familiarity with Linux OS environments
  • Experience with scripting languages such as Bash, Perl, Python, or Tcl
  • Ability to obtain and maintain US Security Clearance

Who We Are, What We Stand For

MissionHires is the AI hiring partner of top talent teams. Our platform helps recruiters, agencies, and top companies source, engage with, and evaluate top talent 10 times faster than job boards.

To bridge the gap between companies and passionate talent.

Frequently Asked Questions

It’s on-site in Rochester, NY.

Yes, paid relocation assistance is provided.

USD $120,000 to $180,000 per year.

Yes, you must be able to obtain and maintain US Security Clearance.

SystemVerilog with UVM/OVM, advanced functional coverage tools, and Mentor Graphics verification tools.

Building self-checking UVM/SystemVerilog testbenches, writing randomized and directed tests, driving functional coverage, and collaborating on embedded communication systems.

SystemVerilog, plus scripting in Bash, Perl, Python, or Tcl; OOP experience in C++ or Java is a plus.

Bachelor’s with 6+ years, or Master’s with 4+ years, or 10+ years relevant experience without a degree.